1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having gate insulating films made of insulating materials which differ between an N-type MISFET and a P-type MISFET, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
To further increase the packaging density and processing speed of a semiconductor integrated circuit device, the size of an MISFET is being decreased, and a gate insulating film made of a high-k material, such as, representatively, alumina (Al2O3), hafnia (HfO2), or hafnium silicate (HfSiOx), is being developed toward commercialization instead of a conventional gate insulating film made of a silicon oxide film (or a silicon oxynitride film). Since such a high-k film has a considerably higher permittivity than that of the silicon oxide film, the physical film thickness can be caused to be thicker, thereby making it possible to avoid a problem that gate leakage current increases with a decrease in film thickness of the gate insulating film made of the silicon oxide film. However, when a polysilicon film is used as a gate electrode which is formed on the gate insulating film of the high-k film, a threshold voltage is shifted due to a phenomenon called Fermi level pinning (see, for example, Non-Patent Document 1: C. Hobbs et al., “Fermi Level Pinning at the PolySi/Metal Oxide Interface”, VLSI Tech. Digest 2003), so that device performance is deteriorated, particularly in P-type MISFETs. Therefore, the high-k film can be used as a gate insulating film which is used in N-type MISFETs (hereinafter referred to as N-type MIS transistors), but not as a gate insulating film which is used in P-type MISFETs (hereinafter referred to as P-type MIS transistors) (i.e., gate insulating films made of different insulating materials need to be separately formed in the N-type MIS transistor and the P-type MIS transistor).
An MISFET which has a metal gate electrode made of a metal film has attracted attention as a solution to problems that the depletion-layer capacitance of a polysilicon gate electrode becomes significant and boron penetrates into the channel region due to a very thin thickness of the gate insulating film.
When a polysilicon film is used as a gate electrode, an n-type impurity is implanted into a polysilicon gate electrode included in the N-type MIS transistor, and a p-type impurity is implanted into a polysilicon gate electrode included in the P-type MIS transistor, thereby providing a dual-gate structure. In contrast, when a metal film is used as a gate electrode, separate metal gate electrodes are formed in the N-type MIS transistor and the P-type MIS transistor, thereby providing a dual-metal gate structure.
By thus employing metal gate electrodes made of metal materials differing between the N-type MIS transistor and the P-type MIS transistor, the work function of the metal gate electrode is controlled, depending on the conductivity type of the MIS transistor (see, for example, Non-Patent Document 2: S. B. Samavedam et al., “Dual-Metal Gate CMOS with HfO2 Gate Dielectric”, IEDM Tech. Digest 2002 and Non-Patent Document 3: Z. B. Zhang et al., “Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric”, VLSI Tech. Digest 2005). Also, the work function of the metal gate electrode material strongly depends on the gate insulating film material. Therefore, in order to improve the performance of the MIS transistor, the individual gate insulating films can be individually optimized for the N-type MIS transistor and the P-type MIS transistor (see, for example, Non-Patent Document 4: S. C. Song et al., “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration”, VLSI Tech. Digest 2006).
However, when gate insulating films made of insulating materials differing between the N-type MIS transistor and the P-type MIS transistor are formed separately, the following problem arises.
Here, the following method is contemplated as a method for forming gate insulating films separately for the N-type MIS transistor and the P-type MIS transistor.
A gate insulating film forming film for the N-type MIS transistor (hereinafter simply referred to as “for nMIS”) is formed on an entire surface of a semiconductor substrate. Thereafter, a resist is formed on the gate insulating film forming film for nMIS, covering an N-type MIS forming region while leaving a P-type MIS forming region exposed. Thereafter, etching is performed using the resist as a mask to remove a portion of the gate insulating film forming film for nMIS which is exposed through the opening of the resist, followed by ashing to remove the resist. Thus, the gate insulating film forming film for nMIS is formed on the N-type MIS forming region in a semiconductor substrate (the gate insulating film forming film for nMIS will become a gate insulating film for nMIS by patterning in a subsequent step, though not described).
Next, a gate insulating film forming film for the P-type MIS transistor (hereinafter simply referred to as “for pMIS”) is formed on an entire surface of the semiconductor substrate. Thereafter, a resist is formed on the gate insulating film forming film for pMIS, covering the P-type MIS forming region while leaving the N-type MIS forming region exposed. Thereafter, etching is performed using the resist as a mask to remove a portion of the gate insulating film forming film for pMIS which is exposed through the opening of the resist, followed by ashing to remove the resist. Thus, the gate insulating film forming film for pMIS is formed on the P-type MIS forming region in the semiconductor substrate (the gate insulating film forming film for pMIS will become a gate insulating film for pMIS by patterning in a subsequent step, though not described).
Note that, in the method above, when the portion of the gate insulating film forming film for pMIS which is exposed through the opening of the resist (in other words, a portion of the gate insulating film forming film for pMIS which is formed on the gate insulating film forming film for nMIS) is removed by etching, it is considerably difficult to selectively remove only the gate insulating film forming film for pMIS without removing the gate insulating film forming film for nMIS below the gate insulating film forming film for pMIS. Therefore, the gate insulating film for nMIS cannot be formed with high accuracy, likely leading to a deterioration in device characteristics of the N-type MIS transistor.
Note that, in the method above, it has been assumed as a specific example that the gate insulating film forming film for pMIS is formed after formation of the gate insulating film forming film for nMIS. Conversely, when the gate insulating film forming film for nMIS is formed after formation of the gate insulating film forming film for pMIS, the gate insulating film for pMIS cannot be formed with high accuracy, likely leading to a deterioration in device characteristics of the P-type MIS transistor.
Also in the method above, when the resist on the gate insulating film forming film for nMIS is removed by ashing, the gate insulating film forming film for nMIS below the resist is damaged, likely leading to an increase in interface level of the gate insulating film for nMIS, and therefore, a deterioration in device characteristics of the N-type MIS transistor. In addition, when the resist on the gate insulating film forming film for pMIS is removed, the gate insulating film forming film for pMIS below the resist is damaged, likely leading to a deterioration in device characteristics of the P-type MIS transistor. Thus, the gate insulating films for nMIS and pMIS cannot be formed with high accuracy, likely leading to a deterioration in device characteristics of the N- and P-type MIS transistors.